IBIS Macromodel Task Group

Meeting date: 09 Jan 2007

Members (asterisk for those attending):
* Arpad Muranyi, Intel Corp.
* Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
  Doug White, Cisco Systems
  Hemant Shah, Cadence Design Systems
* Ian Dodd, Mentor Graphics
* Joe Abler, IBM
* John Angulo
  John Shields, Mentor Graphics
  Ken Willis, Cadence Design Systems
* Kumar, Cadence Design Systems
* Lance Wang, Cadence Design Systems
* Luis Boluna, Cisco
* Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
  Patrick O'Halloran, Tiburon Design Automation
  Paul Fernando, NCSU
* Randy Wolff, Micron Technology
* Richard Ward, Texas Instruments
  Sanjeev Gupta, Agilent
  Shangli Wu, Cadence
* Todd Westerhoff, SiSoft
* Walter Katz, SiSoft
  Vuk Borich, Agilent
  Vikas Gupta, Xilinx

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Review of ARs:

Mike: update macro library documentation
- Mike sent a sample, Arpad gave feedback.
- Feedback being incorporated, almost done.
- Some concern that Mike does not have the latest model version.
  - Mike checked web against his download area.
  - Arpad will check web against his files.

Todd: dig up material on public domain HSPICE syntax
- Synopsys not ready to put HSPICE syntax in public domain.
- They would benefit if more solutions are built around their syntax.
- But if a faster HSPICE-like engine comes along they are in trouble.
- Could propose BIRD for extensions to SPICE language of [External Circuit].
- Walter: could make syntax violations an ibischk warning only.
- No one actually uses the Berkeley engine.
- The attempt to influence Synopsys is closed.

Arpad: Write parameter passing syntax proposal for a possible BIRD
- Not much progress due to vacation.

Mike: Add Kumar and Hemant to the email list.
- Done

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New Discussion:

Online meeting minutes are not up to date.

AR: Mike post minutes to web site

EETimes articles on SystemVerilog and SystemC
- Richard Goering today. Average speed is 835Mhz.
- SystemC used in EU, SystemVerilog in US.
- Information about use of C is confusing and contradictory.
- Fell into "standard trap" of trying to separate IC and PCB.
- IC EDA Survey
  http://www.eetimes.com/news/design/showArticle.jhtml?articleID=190900760
- PCB EDA Survey
  http://www.eetimes.com/issue/fp/showArticle.jhtml?articleID=191902007
- PCB EDA Respondents' Wishlist
  http://www.eetimes.com/issue/fp/showArticle.jhtml?articleID=191901721

DesignCon:
- Todd is signed up for 1/2 hour presentation.
- No review today.

Cadence BIRD:
- Todd has concerns:
  - Might be methodology-specific.
    - Concerned about flow, not syntax
    - How can we determine this?
      - SiSoft will work it out with Cadence
      - Mentor interested too
  - Model might expose arguments.

Pole-zero vs. Impulse response
- Ian: Can convert impulse response to freq domain as long as it covers
  sufficient time.
- Walter: No such thing as pole-zero format, but impulse is industry standard.
- Kumar: impulse and frequency response are equivalent, it does not take
  less points in one format to convey the same information.

Question came up last time and was deferred to this meeting:
  "Do we need an API for TX?"
- Barry: should be able to model TX without an API
  - Only need #taps, timing, coeffs
- Joe: TX needs to adapt also to get optimum bit error rate
- Mirmak: are we trying to simulate this behavior on the fly?
  - Sometimes we know what the system looks like apriori
  - Barry: 
  - Joe: need to simulate adaption process
    eg.: fractionally spaced FFEs, jitter duty cycle, PAM, dual-binary
- Is the method proposed in the BIRD implementation-specific?
  Barry: TX: yes, RX: maybe
  Kumar: no
  Ian: no comment
- Todd: How much wave data is passed into model with each GetWave() call?
  Kumar: not specified
  Todd: the model needs to know, and needs a certain amount to do freq domain.
- Ian: need to provide high res data for 10Gb in time domain. In freq domain
     a smaller number of points are needed.
  Kumar: time points and frequency points convey equivalent data

These meetings are not long enough, should we meet at DesignCon?
- Whiteboard and all
- Thursday night?
  - Wed would be better for some
  - Can't be while the floor is open
- Mentor will provide conference room and food
- Or we could stay in the IBIS room

Who is going to DesignCon IBIS summit?
- yes: Ian, Richard, 4 from SiSoft, Mike L.
- no: Joe Abler

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Next meeting: Tuesday 16 Jan 2006 12:00pm PT